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World IP Day 2026 — Recognized Innovator

Rabin Sugumar

  • Co-Founder & CEO
  • Akeana, Inc.

Recognized as the co-founder and named inventor at Akeana, where his team is building high-performance RISC-V cores. His work spans pipeline architecture, cache design, and simultaneous multi-threading, now licensed to semiconductor companies building chips for AI, automotive, mobile, and datacenter applications. 

Certificate of Recognition

Top IP Innovator — RISC-V Processor Architecture · 2026

Akeana Patents (last 5 years)
0
First Filing
2022
USPTO Art Unit Focus
2136 / 2139
Role
Co-Founder & CEO
Presented by InspireIP

World IP Day Recognition Series · 2026

Akeana patents, last 5 years
0
Filed in 2025 alone
0
Recognition category
0 Semiconductors
The Recognition

Bringing server-class performance to RISC-V

On World IP Day 2026, InspireIP recognizes Rabin Sugumar, co-founder and CEO of Akeana, for his technical leadership in processor architecture.

The recognition is based on Akeana’s patent activity and public patent records where Rabin is named as an inventor. His filings cover out-of-order processor pipelines, cache prefetching, data stream detection, simultaneous multi-threading, and instruction handling for mixed floating-point and integer operations.

Rabin holds a PhD in Computer Science and Engineering from the University of Michigan, where his doctoral work included a cache simulator still used in academic research.

Before co-founding Akeana in 2021, he spent more than 25 years in CPU architecture, including work on high-performance Arm server processors. At Akeana, that experience now supports the company’s work in RISC-V processor design.

RISC-V Processors
Out-of-Order Execution
Simultaneous Multi-Threading
Cache Architecture
Server-Class Compute
AI Acceleration
Patent Footprint

A portfolio shaped around processor performance

2021

Rabin Sugumar co-founds Akeana in Santa Clara, California, assembling much of the former Cavium/Marvell ThunderX2 engineering team. The company begins developing RISC-V processor IP in stealth mode.

2022–2023

The patent portfolio grows rapidly, with 31 filings across two years, peaking at 23+ filings in 2023. The filings cover core processor architectures across Akeana's three product families: the 100 series (embedded), 1000 series (mid-range), and 5000 series (high-performance application processors).

2024

15 more patents filed as Akeana exits stealth in August, announces $100M+ in funding, and launches its full processor and system IP portfolio for licensing.

2025

5 additional filings. Akeana tapes out Alpine, its highest-performance server-class test chip, built in 4nm and RVA23-compatible. The company demonstrates simultaneous multi-threading at the RISC-V Summit in Santa Clara and partners with proteanTecs and Axiomise for reliability and formal verification.

RISC-V Processor Architecture

A small-entity company filing like a much larger one

Akeana is classified by the USPTO as a Small Entity, yet its five-year filing volume sits well above what is typical for semiconductor IP startups of its size. Much of that activity is concentrated in the computer architecture and security art units that protect processor pipeline designs, cache hierarchies, and multi-threading systems.

Patents, last 5 years
Peak year (2023)
Filings
USPTO entity status
Small Entity
Art unit focus
2136 / 2139
"Leading an innovation program is harder than inventing on your own. It means choosing what to file, who to credit, and where to invest, over and over, for years. The leaders we recognize on World IP Day have done that consistently, and built something that compounds."

Sam Zellner

Founder, InspireIP · Inventor · Innovation Leader

About Akeana

Built in Santa Clara, licensing processor IP worldwide

Founded in 2021 and headquartered in Santa Clara, California, Akeana builds high-performance RISC-V processor and system IP for semiconductor companies.

The company’s product range spans embedded microcontrollers, in-order cores, server-class out-of-order application processors, an AI matrix computation engine., to name a few.

Akeana’s engineering team has worked together for more than 20 years and includes architects behind the Cavium and Marvell ThunderX2.

In December 2025, the company taped out Alpine, a 4nm server-class RISC-V test chip and the highest-performance RVA23-compatible chip to date.

IP Day 2027

Know an IP innovator who deserves recognition?

Each year we recognize the inventors and IP leaders behind the portfolios that protect what their companies create. That includes founder-inventors whose contributions often go unmarked. Nominate someone for next year’s list.

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